From patchwork Sun Apr 23 08:04:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arne Fitzenreiter X-Patchwork-Id: 6809 Return-Path: Received: from mail01.ipfire.org (mail01.haj.ipfire.org [172.28.1.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) client-signature ECDSA (P-384)) (Client CN "mail01.haj.ipfire.org", Issuer "R3" (verified OK)) by web04.haj.ipfire.org (Postfix) with ESMTPS id 4Q41513GNgz3x1n for ; Sun, 23 Apr 2023 08:04:37 +0000 (UTC) Received: from mail02.haj.ipfire.org (mail02.haj.ipfire.org [172.28.1.201]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) client-signature ECDSA (P-384)) (Client CN "mail02.haj.ipfire.org", Issuer "R3" (verified OK)) by mail01.ipfire.org (Postfix) with ESMTPS id 4Q414z6qXxz16Y; Sun, 23 Apr 2023 08:04:35 +0000 (UTC) Received: from mail02.haj.ipfire.org (localhost [127.0.0.1]) by mail02.haj.ipfire.org (Postfix) with ESMTP id 4Q414z5l0Rz2y9y; Sun, 23 Apr 2023 08:04:35 +0000 (UTC) Received: from mail01.ipfire.org (mail01.haj.ipfire.org [172.28.1.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) client-signature ECDSA (P-384)) (Client CN "mail01.haj.ipfire.org", Issuer "R3" (verified OK)) by mail02.haj.ipfire.org (Postfix) with ESMTPS id 4Q414y4ypCz2xxK for ; Sun, 23 Apr 2023 08:04:34 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by mail01.ipfire.org (Postfix) with ESMTPSA id 4Q414x2v9lzqj; Sun, 23 Apr 2023 08:04:33 +0000 (UTC) DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=ipfire.org; s=202003ed25519; t=1682237073; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=H4ldg9gHb5bZcQD7d/bBstYv3j3yUbNc6RaginmzJNw=; b=aJ/bDswvu3Rr4sxqT30Cu2sZNzPej1GkPzSARaqsUNtMq9d69+Bt8qVV5k2C9ubERXEHdQ X0t+NPEFmDXClbBQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ipfire.org; s=202003rsa; t=1682237073; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=H4ldg9gHb5bZcQD7d/bBstYv3j3yUbNc6RaginmzJNw=; b=PC/HeJTY/jNCT27pthMU+4YBZjVC4mChZ7OyfW8vO4r5xUJfknyVaBgO9j4KdSoqIuHlqr rNFtx4QlDU/UhPmE9QDHxk7+iL6YcJDWUTOik7JyvmheStsdW6DMQau6eCf8V72oDsffNo gbNrHeGmvlx7saxF1JmlBuZ6D0PKg8kvzaAf8fZpRLsNfeqvfb+XoP/BAVVKUcRz2oDJWp soRqimfkBHJnVWeddHnlyUWsvJwm1ZSVJfICNqR9mjUo6QrBkSynyfkOzkcVMUmSjTL5hJ cZPMXy0b5cTwD2bHR89425ecPnE4w2qjQNuBiC/L3fMZK8JJocF8p9sei9bfMQ== From: Arne Fitzenreiter To: development@lists.ipfire.org Subject: [PATCH] u-boot: add nanopi r2c support Date: Sun, 23 Apr 2023 08:04:22 +0000 Message-Id: <20230423080422.441678-1-arne_f@ipfire.org> MIME-Version: 1.0 X-BeenThere: development@lists.ipfire.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: IPFire development talk List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arne Fitzenreiter Errors-To: development-bounces@lists.ipfire.org Sender: "Development" this patch add nanopi r2c plus support. if this u-boot is installed on the eMMC this is also supported. Signed-off-by: Arne Fitzenreiter --- config/rootfiles/common/aarch64/u-boot | 2 + lfs/u-boot | 20 +++ .../u-boot/rockchip/add_nanopi-r2c.patch | 169 ++++++++++++++++++ .../u-boot/rockchip/generate-2-ethaddr.diff | 18 -- 4 files changed, 191 insertions(+), 18 deletions(-) create mode 100644 src/patches/u-boot/rockchip/add_nanopi-r2c.patch delete mode 100644 src/patches/u-boot/rockchip/generate-2-ethaddr.diff diff --git a/config/rootfiles/common/aarch64/u-boot b/config/rootfiles/common/aarch64/u-boot index 2b60c7802..4b2dcd4fd 100644 --- a/config/rootfiles/common/aarch64/u-boot +++ b/config/rootfiles/common/aarch64/u-boot @@ -6,6 +6,8 @@ boot/u-boot-rpi4.bin boot/uEnv.txt boot/uboot.env #usr/share/u-boot +#usr/share/u-boot/nanopi_r2c +usr/share/u-boot/nanopi_r2c/u-boot-rockchip.bin #usr/share/u-boot/nanopi_r2s usr/share/u-boot/nanopi_r2s/u-boot-rockchip.bin #usr/share/u-boot/nanopi_r4s diff --git a/lfs/u-boot b/lfs/u-boot index 0d4c2cc58..cea74e64c 100644 --- a/lfs/u-boot +++ b/lfs/u-boot @@ -137,6 +137,26 @@ ifneq "$(MKIMAGE)" "1" /usr/share/u-boot/nanopi_r2s/u-boot-rockchip.bin cd $(DIR_APP) && make distclean + # Nanopi R2C + cd $(DIR_APP) && patch -Np1 < $(DIR_SRC)/src/patches/u-boot/rockchip/add_nanopi-r2c.patch + cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER) + cd $(DIR_APP) && tar axf $(DIR_DL)/arm-trusted-firmware-$(ATF_VER).tar.gz + cd $(DIR_APP)/arm-trusted-firmware-$(ATF_VER) && make PLAT=rk3328 ARCH=aarch64 DEBUG=0 bl31 LDFLAGS="$(LDFLAGS)" + cd $(DIR_APP) && cp arm-trusted-firmware-$(ATF_VER)/build/rk3328/release/bl31/bl31.elf bl31.elf + cd $(DIR_APP) && rm -rf arm-trusted-firmware-$(ATF_VER) + -mkdir -pv /usr/share/u-boot/nanopi_r2c + + cd $(DIR_APP) && make CROSS_COMPILE="" nanopi-r2c-rk3328_config + cd $(DIR_APP) && sed -i -e 's!^CONFIG_IDENT_STRING=.*!CONFIG_IDENT_STRING=" Nanopi R2C - IPFire.org"!' .config + cd $(DIR_APP) && sed -i -e 's!^CONFIG_BOOTCOMMAND=.*!CONFIG_BOOTCOMMAND="console=ttyS2,115200n8;run distro_bootcmd"!' .config + cd $(DIR_APP) && sed -i -e 's!^CONFIG_BAUDRATE=.*!CONFIG_BAUDRATE=115200!' .config + cd $(DIR_APP) && sed -i -e 's!.*CONFIG_ENV_OVERWRITE.*!CONFIG_ENV_OVERWRITE=y!' .config + cd $(DIR_APP) && make CROSS_COMPILE="" HOSTCC="gcc $(CFLAGS)" + cd $(DIR_APP) && install -v -m 644 u-boot-rockchip.bin \ + /usr/share/u-boot/nanopi_r2c/u-boot-rockchip.bin + cd $(DIR_APP) && make distclean + + # Nanopi R4S # arm trusted firmware for rk3399 cannot build without cortex m0 gcc crosscompiler # it is build on ubuntu with make PLAT=rk3399 ARCH=aarch64 DEBUG=0 bl31 diff --git a/src/patches/u-boot/rockchip/add_nanopi-r2c.patch b/src/patches/u-boot/rockchip/add_nanopi-r2c.patch new file mode 100644 index 000000000..9e330041f --- /dev/null +++ b/src/patches/u-boot/rockchip/add_nanopi-r2c.patch @@ -0,0 +1,169 @@ +diff -Naur u-boot-2022.10.org/arch/arm/dts/Makefile u-boot-2022.10/arch/arm/dts/Makefile +--- u-boot-2022.10.org/arch/arm/dts/Makefile 2022-10-03 19:25:32.000000000 +0000 ++++ u-boot-2022.10/arch/arm/dts/Makefile 2023-04-22 15:02:25.945603949 +0000 +@@ -124,6 +124,7 @@ + + dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ ++ rk3328-nanopi-r2c.dtb \ + rk3328-nanopi-r2s.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ +diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi +--- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi 2023-04-22 15:07:54.544953841 +0000 +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++#include "rk3328-nanopi-r2s-u-boot.dtsi" +diff -Naur u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c.dts +--- u-boot-2022.10.org/arch/arm/dts/rk3328-nanopi-r2c.dts 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot-2022.10/arch/arm/dts/rk3328-nanopi-r2c.dts 2023-04-22 15:07:07.861614679 +0000 +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++/dts-v1/; ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R2C"; ++ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; ++}; ++ ++&emmc { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ max-frequency = <150000000>; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; ++ vmmc-supply = <&vcc_io_33>; ++ vqmmc-supply = <&vcc18_emmc>; ++ status = "okay"; ++}; +diff -Naur u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig +--- u-boot-2022.10.org/configs/nanopi-r2c-rk3328_defconfig 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot-2022.10/configs/nanopi-r2c-rk3328_defconfig 2023-04-22 15:09:20.843584447 +0000 +@@ -0,0 +1,112 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x2000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x2000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK=0x400000 ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSINFO=y ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/src/patches/u-boot/rockchip/generate-2-ethaddr.diff b/src/patches/u-boot/rockchip/generate-2-ethaddr.diff deleted file mode 100644 index 067c8b503..000000000 --- a/src/patches/u-boot/rockchip/generate-2-ethaddr.diff +++ /dev/null @@ -1,18 +0,0 @@ -diff -Naur u-boot-2021.07.org/arch/arm/mach-rockchip/misc.c u-boot-2021.07/arch/arm/mach-rockchip/misc.c ---- u-boot-2021.07.org/arch/arm/mach-rockchip/misc.c 2021-07-05 15:11:28.000000000 +0000 -+++ u-boot-2021.07/arch/arm/mach-rockchip/misc.c 2021-10-08 10:47:13.704806367 +0000 -@@ -49,9 +49,12 @@ - memcpy(mac_addr, hash, 6); - - /* Make this a valid MAC address and set it */ -- mac_addr[0] &= 0xfe; /* clear multicast bit */ -- mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ -+ mac_addr[0] = 0x02; /* set local assignment bit (IEEE802) */ - eth_env_set_enetaddr("ethaddr", mac_addr); -+ if (env_get("eth1addr")) -+ return 0; -+ mac_addr[0] = 0x12; /* set local assignment bit (IEEE802) */ -+ eth_env_set_enetaddr("eth1addr", mac_addr); - #endif - return 0; - }